This invention is generally related to an embedded dynamic random access memory (embedded DRAM), and more particularly, to a structure and a method for providing an in-macro redundancy allocation during a multi-bank operation by sampling a pass/fail detection.
Improvements in semiconductor technology have enabled processors to operate at a frequency exceeding 1 Giga Hz. However, the processor performance is often limited by the performance of its memory. This has created a potential strong demand for high performance embedded Dynamic Random Access Memories (DRAMs) to match the processor speed. Embedded DRAMs, however, require a write back operation when accessing a memory cell, which slows the random access cycle time when compared to an embedded SRAM lacking the write-back operation. This drawback is typically overcome by a multi-bank operation.
FIG. 1 shows a schematic block diagram that illustrates the architecture of a conventional DRAM device. DRAM 100 consists of a plurality of memory arrays 110, each array consisting of a plurality of memory cells 120 arranged in a matrix. The memory cells in the array are supported by a plurality of wordlines 130 and bitlines 140. The cells in the memory array are accessed by activating wordline 130. When the wordline, e.g., in array 110A is energized, the data bits in all the cells 120 coupled to, e.g., wordline 130 are read out to bitlines 140. The read data bits are then amplified by a sense amplifier (not shown) enabling the bits to be read out to datalines 150 by coupling bitlines 140 to data lines 150 by way of switches 142. Datalines 150 are typically arranged throughout the arrays 110, enabling data to be read from or written to any of the arrays 110. The data bits read out from the memory cells are subsequently written back to the cells 120 by making use of the bitline swing resulting from a sensing operation, since data in the cell data is destroyed when wordline 130 is activated (i.e., destructive read and write back operations). Memory array 110A remains active as long as the write back operation is in progress. The memory access cycle time is limited by destructive read out and write back operations, which will be referred to hereinafter as the random access cycle time. During a memory access operation in memory array 110A, other memory arrays, such as 110B, may initiate a memory access operation. By staggering the n memory array accesses during the random access cycle time, the data rate improves by a factor n times the data rate of the individual memory array. The cycle time in the aforementioned multi-bank operation is referred to as a bank-to-bank access cycle time.
Multi-bank operations create a problem when allocating redundancies in situations where the memory arrays during a multi-bank operation consist of two or more domains, which will be explained hereinafter. By way of example, memory array 110A is provided with a row redundancy 130R that repairs a fail occurring in memory array 110A (to be referred as domain A). Similarly, memory array 110B includes a row redundancy 130R that repairs a fail in memory array 110B (to be referred as domain B). Note that the redundancy replacement for memories 110A and B (domains A and B) differ from one another.
During a multi-bank test operation, a fail detected by the redundancy allocation logic will be ‘seen’ in two domains when the memory arrays (110A and 110B) that are supported by the two domains A and B are addressed. This makes it difficult to assign a redundancy replacement using redundancy allocation logic, unless the redundancy allocation logic has a function that identifies the domain for each detected fail. Because the multi-bank typically operates in the range of 500 MHz, enabling this function becomes very difficult.
Handling of the redundancy allocations during a multi-bank operation having two or more domains is complicated by the fact that the redundancy allocation needs to be completed within the bank-to-bank-access cycle time. Typically, the redundancy allocation, particularly when assigning a row redundancy requires the use of OR logic, which is inherently slow and which significantly exceeds the bank-to-bank-access cycle time. A pipeline architecture commonly used for a processor may improve the speed of the redundancy allocation logic by dividing a redundancy allocation cycle into many small pipeline cycles to support several bank allocations. However, this is a complex and expensive process. Therefore, the existing redundancy allocation logic, applicable to a conventional embedded DRAM prohibits a multi-bank operation when the redundancy allocation takes place, in which only one bank is allocated at a time. However, this is not a precondition set for the application and, therefore, it is not an ideal solution for high speed multi-bank operations.